Conventional interconnect structures for integrated circuits are often formed using aluminum as a metallization layer and silicon dioxide as a dielectric. However, while integrated circuits are being continuously scaled down (such as device scaling from the 90 nm node to the 65 nm node and further to the 45 nm node), conventional interconnect structures often suffer from an interconnection delay due to high electrical resistance and parasitic wiring capacitance. These problems are major factors that limit the speed of high performance integrated circuits.
Integrated circuit manufacturers have begun using copper in place of aluminum and a low-K material in place of silicon dioxide in the interconnect structures to address these issues. The copper helps to lower the resistance of the interconnect metallization and increase the reliability of the interconnect structures, while the low-K material helps to reduce the parasitic capacitance between the interconnect structures by providing a lower dielectric constant. However, the ability to reduce the dielectric constant of the low-K material is typically limited, and low-K materials are often mechanically weak.